DS26502DK
Register Name: LEVEL4
Register Description: DS26502 Pin Settings (TSM, TITD)
Register Offset: 0x0014
Bit #
Name
Default
7
0
6
0
5
TSMtri
0
4
TSM_Lev
0
3
0
2
0
1
TITDtri
0
0
TITD_Lev
0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 5 and 4: DS26502 TSM Tri-State and Level (TSMtri and TSM_Lev)
00 = FPGA drives TSM with 0V
01 = FPGA drives TSM with 3.3V
1x = FPGA tri-states TSM pin
Bits 1 and 0: DS26502 TITD Tri-State and Level (TITDtri and TITD_Lev)
00 = FPGA drives TITD with 0V
01 = FPGA drives TITD with 3.3V
1x = FPGA tri-states TITD pin
Register Name: LEVEL5
Register Description: DS26502 Pin Settings (TCSS1, TCSS0)
Register Offset: 0x0015
Bit #
Name
Default
7
0
6
0
5
TCSS1tri
0
4
TCSS1_Lev
0
3
0
2
0
1
TCSS0tri
0
0
TCSS0_Lev
0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 5 and 4: DS26502 TCSS1 Tri-State and Level (TCSS1tri and TCSS1_Lev)
00 = FPGA drives TCSS1 with 0V
01 = FPGA drives TCSS1 with 3.3V
1x = FPGA tri-states TCSS1 pin
Bits 1 and 0: DS26502 TCSS0 Tri-State and Level (TCSS0tri and TCSS0_Lev)
00 = FPGA drives TCSS0 with 0V
01 = FPGA drives TCSS0 with 3.3V
1x = FPGA tri-states TCSS0 pin
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相关PDF资料
DS26503DK KIT DESIGN FOR DS26503
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相关代理商/技术参数
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